Intellectual Property

Trademarks

Abacus Semiconductor Corporation™ and the Abacus Semiconductor Corporation Logo as well as ASC-LSS™ (ASC Legacy Support System), ASC-AP™ (ASC Application Processor), ASC-DP™ (ASC Database Processor), ASC-MP™ (ASC Math Processor) and ASC-HRAM™ (ASC Hybrid RAM) as well as

  • Universal High-Performance Interconnect/UHI™
  • Latency-Reduced SerDes/LRS™
  • Multi-Homed Memory Architecture/MHMA™
  • Autonomous Memory Command Processor/AMCP™
  • Memory-Internal TLB/MITLB™
  • Hardware Assisted Virtualization/HAV™
  • Contention-Reduced Switch Fabric/CRSF™
  • Assured Firmware Integrity/AFI™
  • Resilient Secure Boot/RSB™
  • Protected Shadow ROM/PSR™
  • Zero Thread MemCopy/ZTM™
  • IPC Acceleration/IPCA™
  • Interrupt Request Mitigation/IRM™
  • Secure DMA/SDMA™
  • I/O Pre-Processing/IOPP™
  • Secure Data Transfer Offload/SDTO™

are trademarks or pending trademarks of Abacus Semiconductor Corporation and/or its affiliates.

Patents

Abacus Semiconductor Corporation has applied for a number of patents at the USPTO and the European Patent Office as well as other select international Patent Offices.

  • We have submitted our first omnibus patent application for our Kloth Architecture that goes beyond the established von-Neumann and Harvard architectures. This "Kloth Architecture" extends the well-known Harvard architecture by adding a scale-out port dedicated to the interconnection of processor and accelerator cores across packages, thereby enabling the "Heterogeneous Accelerated Compute" as described in patent (US 2025/0036589 A1). The "Heterogeneous Accelerated Compute" addresses shortcomings in today's architectures by allowing for a direct and universal connectivity between processor cores and accelerator cores via UHI, and thereby reduces latency between any two elements by a factor of 3 to 30. This kind of latency reduction allows for a much more seamless integration of accelerators with processors, increasing the performance that is available to the user, minimizing power consumption, and simplying APIs instead of Instruction Set Architectures.
  • Look out for more announcements soon.