The Database Processor is a CPU with 64 RISC-V cores (v1 prototype) and 16 UHI ports. All RISC-V processor cores are 64-bit variants with hardware support for virtualization and vastly optimized internal interconnects. The ASC-DP is also referred to as the ASC29300. In a typical deployment, the ASC-DP is used with at least one ASC-LSS as an I/O frontend through one of its UHI ports. All other UHI ports can be used to connect to other Database Processors and Heterogeneous Random Access Memories, and at least one Application Processor for orchestration and for optional connection to additional legacy I/O through the Server-on-a-Chip or ASC-LSS. The target deployment scenarios of this processor are large-scale in-memory database applications.

It offers all of our advanced technology, such as Universal High-Performance Interconnect/UHI™, Assured Firmware Integrity/AFI™ and Zero Thread MemCopy/ZTM™ support within our Heterogeneous Random Access Memory. We have added hardware to the CPU cores to support virtualization so that they can be used in fully virtualized environments.

These processors are part of our Heterogeneous Accelerated Compute initiative. In this novel system architecture for AI and HPC, all processor and accelerator cores are connected directly to each other, even across packages and from processor to accelerator and vice versa, to facilitate lower-latency communication across all cores, extending our Kloth Architecture to beyond-von-Neumann and beyond-Harvard CPU scalability and seamless integration. More information about this novel architecture is available at the USPTO under patent US 2025/0036589 A1. This patent extends to the integration of our Smart Multi-Homed Memory as well, to enable shared memory and the Message Passing Interface (MPI).

These comprehensive subsystems include dedicated processors, firmware, software and APIs as well as SDK plugins. We are working on native implementations of in-memory databases and MariaDB, MySQL and a variety of other applications that make use of the extremely high transaction count that this processor provides in conjunction with the Heterogeneous Random Access Memory and the Application Processor as well as the Server-on-a-Chip (ASC-LSS) as an I/O frontend for legacy mass storage and for PCIe Gen3.