The Application Processor is a CPU with 64 RISC-V cores (v1 prototype) and 16 UHI ports. All RISC-V processor cores are 64-bit variants with hardware support for virtualization and vastly optimized internal interconnects. The ASC-AP is also referred to as the ASC29200. In a typical deployment, the ASC-AP is used with at least one ASC-LSS as an I/O frontend through one of its UHI ports. All other ports can be used in a mix-and-match configuration to connect to other Application Processors, Database Processors, Math Processors or Heterogeneous Random Access Memories. The target deployment scenarios of this processor are applications in which a strict centralized scheduling of tasks is performed by an application processor and the work is offloaded to other processors, coprocessors or specific accelerators. At this point in time, the Application Processor is based on the same processor die as the Database Processor, but the firmware is different. In the future, the hardware of these two processor families may diverge.

These processors are part of our Heterogeneous Accelerated Compute initiative. In this novel system architecture for AI and HPC, all processor and accelerator cores are connected directly to each other, even across packages and from processor to accelerator and vice versa, to facilitate lower-latency communication across all cores, extending our Kloth Architecture to beyond-von-Neumann and beyond-Harvard CPU scalability and seamless integration. More information about this novel architecture is available at the USPTO under patent US 2025/0036589 A1. This patent extends to the integration of our Smart Multi-Homed Memory as well, to enable shared memory and the Message Passing Interface (MPI).

These processors do not exist as a category right now. We will - as we have shown before - introduce new categories of processors as needed.

These comprehensive subsystems include dedicated processors, firmware, software and APIs as well as SDK plugins.